Recently, technology using a laser to replace defective elements by redundant (spare) rows or columns has been developed. A pioneer work of such device is reported in an article "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM", IEEE J. Solid-State Circuits, vol. SC-16, pp. 506-513, Oct. 1981 by R. T. Smith et al.
This article points out the following three items as problems in irradiating a laser beam to a link element, which are especially important in highly integrated circuits:
(1) laser spot size,
(2) dimension of the link element, and
(3) distance between the link elements.
Further prior art relating to such technology is reported in an article "A 256K Dynamic RAM with Page-Nibble Mode", IEEE J. Solid-State Circuits, vol. SC-18, pp. 470-478, Oct. 1983, by K. Fujishima et al.
FIG. 1(a) and (b) are schematic diagrams showing the row decoder and the spare row decoder of the semiconductor memory device with laser programmable redundancy construction shown in the article. In the row decoder for selecting a word line shown in FIG. 1(a), the reference numerals 1a.sub.1 to 1a.sub.n-1 designate address signal lines to which the address signals A.sub.1 or A.sub.1 to A.sub.n-1 or A.sub.n-1 are input. The reference numerals 2a.sub.a to 2a.sub.n-1 designate transistors to the gates whereof the address signals A.sub.1 or A.sub.1 to A.sub.n-1 or A.sub.n-1 are input. The reference numeral 3 designates a decoder output line. The numeral 4 designates a RAS signal line to which the row address strobe (RAS) signal shown in FIG. 2(a) is input. The numeral 5 designates a transistor to the gate whereof the RAS signal is input. The numeral 6 designates a power supply line of voltage V.sub.DD. The numerals 7a and 7b designate RXD signal lines to which the RXD signal for separating the decoder and the word line shown in FIG. 2(f) is input. The reference numerals 8a.sub.0 and 8a.sub.1, 8b.sub.0 and 8b.sub.1 designate RX.sub.0 and RX.sub.1 signal lines, respectively, to which the sub-decode signals RX.sub.0 and RX.sub.1 (refer to FIG. 2(d)) generated from the word line driving signal (RX signal) are input, respectively. The reference numerals 9a and 9b designate RQ signal lines to which the RQ signal for clamping the unselected word line to the ground level shown in FIG. 2(g) is input. The reference numerals 10a and 10b designate the n-th left word line (referred also as WLL.sub.n) and the n-th right word line (referred also as WLR.sub.n). The numerals 11a and 11b designate the (n+1)-th left and right word lines (WLL.sub.n+1, WLR.sub.n+1). The reference numerals 12a to 12c, 13a to 13c, 14a to 14c, and 15a to 15c designate transistors. The reference numerals 16a to 16d designate link elements which will be melted by a laser beam when the memory cells selected by the word lines are faulty so as to make the faulty word lines unselected.
Furthermore, in the spare decoder shown in FIG. 1(b), the reference numerals 17a.sub.1, 17b.sub.1, to 17a.sub.n-1, 17b.sub.n-1 designate address signal lines to which the address signals A.sub.1, A.sub.1 to A.sub.n-1, A.sub.n-1 are input. The reference numerals 18a, 18b to 18a.sub.n-1, 18b.sub.n-1 designate transistors to the gate whereof the address signals A.sub.1, A.sub.1 to A.sub.n-1, A.sub.n-1 are input. The numerals 19a, 19b to 19a.sub.n-1, 19b.sub.n-1 designate link elements. The numeral 20 designates a decoder output line. The numeral 21 designates a RAS signal line to which the RAS signal is input. The numeral 22 designates a transistor to the gate whereof the RAS signal is input. The numeral 23a and 23b designate RXD signal lines to which the RXD signal for separating the decoder and the word line is input. The numerals 24a.sub.0, 24a.sub.1 and 24b.sub.0, 24b.sub.1 designate RX.sub.0 and RX.sub.1 signal lines to which the sub-decode RX.sub.0 and RX.sub.1 signals are input, respectively. The numerals 25a and 25b designate RQ signal lines to which the RO signal is input. The numerals 26a and 26b designate first left and right word lines (referred also as WLL.sub.s0, WLR.sub.s0). The numerals 27a and 27b designate second left and right word lines (referred also as WLL.sub.s1, WLR.sub.s1). The numerals 28a to 28c, 29a to 29c, 30a to 30c, and 31a to 31c designate transistors, and the numerals 32a to 32d designate link elements.
The device will be operated as follows:
At first, pre-chargings of all the decoders are executed while the RAS signal shown in FIG. 2(a) is at "H" level. After the RAS signal becomes "L" level, an address is selected. For example, the address signals Ai, Ai shown in FIG. 2(b) are generated, and the output lines 3 of all the decoders except for the selected decoder are discharged. The output line 3 of the selected decoder is maintained at "H" level, and the word lines at the left and right side of the decoder are selectively driven by the sub-decode RX.sub.0 or RX.sub.1 signals (refer to FIG. 2(d) which shows a case where decoded by the signal A.sub.0) generated from the word line driving RX signal shown in FIG. 2(c). The word line driving WL signal which is selectively driven becomes "H" level as shown in FIG. 2(e). When the memory cell (not shown) selected by the word line has a fault, the link element which is connected to the word line is melted by a laser beam, thereby making the word line unselected. On the other hand, in the spare decoder shown in FIG. 1(b), the link element which corresponds to each bit of the address of the faulty memory cell, that is, either of each pair of link elements 19a and 19b to 19n.sub.a-1 and 19b.sub.n-1 is melted by a laser beam, and the row decoder which is connected to the faulty word line is replaced by the spare row decoder.
Under the semiconductor memory device of such construction, however, the link element for separating the faulty word line from the decoder and making the faulty word line unselected must be provided for each word line. Accordingly, in a highly integrated memory device such as a dynamic RAM having more than 256K or 1M bits the requirements for the positioning accuracy of the laser beam and the laser spot size become severe, thereby making it difficult to realize the same in practical use.
Another prior art device is reported in an article "A Low-Power Sub 100ns 256K Bit Dynamic RAM", IEEE J. Solid-State Circuits, vol. SC-18, pp. 441-446, Oct. 1983, by S. Fujii et al. In this device, a link element is not provided for each word line, being appropriate for high integration. However, the operational speed is disadvantageously low.